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Syllabus ( ELEC 457 )

   Basic information
Course title: FPGA-based system design
Course code: ELEC 457
Lecturer: Dr. Furkan ÇAYCI
ECTS credits: 6
GTU credits: 3 ()
Year, Semester: 4, Fall
Level of course: First Cycle (Undergraduate)
Type of course: Area Elective
Language of instruction: English
Mode of delivery: Face to face , Group study , Lab work
Pre- and co-requisites: ELM 234, ELM 235
Professional practice: No
Purpose of the course: FPGA-based System Design examines modern digital computer design methods using industry standard electronic CAD synthesis tools. Topics include hardware design, logic synthesis tools, simulation methods for synthesis and efficient coding techniques for synthesis. Includes experimental laboratory work to design and evaluate FPGA-based digital computer hardware. Two projects will be given.

At the end of this course, students should be able to design, code, synthesize and test a complete digital design using HDL simulation and synthesis tools and FPGA devices. This course uses industry-standard design tools and FPGA devices. Depending on the semester different hardware languages such as VHDL, Verilog, or SystemVerilog might be used.
   Learning outcomes Up

Upon successful completion of this course, students will be able to:

  1. Design, implement and validate a project into hardware logic for FPGAs

    Contribution to Program Outcomes

    1. Perform systems design, maintenance and development
    2. Develop his/her knowledge in using different techniques and modern equipment for engineering applications
    3. Employ modern techniques and operate technical devices

    Method of assessment

    1. Term paper
  2. Validate hardware logic to verify timing and accuracy using created testbenches.

    Contribution to Program Outcomes

    1. Design and conduct experiments, as well as analyze and interpret data
    2. Formulate and solve engineering problems
    3. Develop his/her knowledge in using different techniques and modern equipment for engineering applications

    Method of assessment

    1. Written exam
    2. Laboratory exercise/exam
  3. Utilize commercial FPGA development tools for simulation and synthesis of projects.

    Contribution to Program Outcomes

    1. Perform systems design, maintenance and development
    2. Develop his/her knowledge in using different techniques and modern equipment for engineering applications
    3. Employ modern techniques and operate technical devices

    Method of assessment

    1. Laboratory exercise/exam
    2. Term paper
   Contents Up
Week 1: Introduction to course, digital design review
Week 2: Overview of FPGAs, FPGA design flow
Week 3: Introduction to HDLs
Week 4: Combinational logic
Week 5: Sequential logic
Week 6: Finite State Machines
Week 7: Memory, FIFO design
Week 8: Timing, Critical Path
Week 9: Clock Domain Crossings
Week 10: Speed Optimizations
Week 11: Embedded System Design flow with FPGAs
Week 12: Zynq Architecture
Week 13: Interconnects & Debugging
Week 14: Project Presentations
Week 15*: *
Week 16*: Final
Textbooks and materials: The Designer’s Guide to VHDL, Peter J. Ashenden
HDL Chip Design, Douglas J. Smith
Advanced FPGA Design Architecture, Implementation, and Optimization, Steve Kilts
Recommended readings: The Zynq Book
Online materials and examples
  * Between 15th and 16th weeks is there a free week for students to prepare for final exam.
Assessment Up
Method of assessment Week number Weight (%)
Mid-terms: - 0
Other in-term studies: - 0
Project: 4,5,6,7,8,9,10,11,12,13,14 40
Homework: 2, 4, 6, 8 10
Quiz: 4, 8, 10 10
Final exam: 16 40
  Total weight:
(%)
   Workload Up
Activity Duration (Hours per week) Total number of weeks Total hours in term
Courses (Face-to-face teaching): 3 14
Own studies outside class: 4 14
Practice, Recitation: 0 0
Homework: 4 4
Term project: 11 2
Term project presentation: 1 1
Quiz: 1 3
Own study for mid-term exam: 0 0
Mid-term: 0 0
Personal studies for final exam: 8 1
Final exam: 2 1
    Total workload:
    Total ECTS credits:
*
  * ECTS credit is calculated by dividing total workload by 25.
(1 ECTS = 25 work hours)
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